THE TECHNOLOGY-PUSH OF DIE STACKING AND APPLICATION-PULL OF BIG DATA MACHINE LEARNING ANALYTICS (BMLA) HAVE CREATED A UNIQUE OPPORTUNITY FOR PROCESSING-NEAR-MEMORY (PNM). THIS PAPER MAKES FOUR CONTRIBUTIONS: (1) WHILE PREVIOUS PNM WORK EXPLORES GENERAL MAPREDUCE WORKLOADS, WE IDENTIFY THREE APPLICATION CHARACTERISTICS OF MOST BMLAS: (A) IRREGULAR-AND-COMPUTE-LIGHT (I.E., PERFORM ONLY A FEW OPERATIONS PER INPUT WORD WHICH INCLUDE DATA-DEPENDENT BRANCHES AND INDIRECT MEMORY ACCESSES); (B) COMPACT (I.E., THE RELEVANT PORTION OF THE INPUT DATA AND THE INTERMEDIATE LIVE DATA FOR EACH THREAD ARE SMALL); AND (C) MEMORY-ROW-DENSE (I.E., PROCESS THE INPUT DATA WITHOUT SKIPPING OVER MANY BYTES). THESE CHARACTERISTICS, EXCEPT FOR IRREGULARITY, ARE NECESSARY FOR BANDWIDTH-AND ENERGY-EFFICIENT PNM, IRRESPECTIVE OF THE ARCHITECTURE. (2) BASED ON THESE CHARACTERISTICS, WE PROPOSE MEMORY OPTIMIZATIONS FOR A "SEA OF SIMPLE MIMD CORES (SSMC)" PNM ARCHITECTURE, CALLED MILLIPEDE, WHICH (PRE) FETCHES AND OPERATES ON ENTIRE MEMORY ROWS TO EXPLOIT BMLAS' ROW-DENSITY. INSTEAD OF THIS ROW-ORIENTED ACCESS AND COMPUTE-SCHEDULE, TRADITIONAL MULTICORES OPPORTUNISTICALLY IMPROVE ROW LOCALITY WHILE FETCHING AND OPERATING ON CACHE BLOCKS. (3) MILLIPEDE EMPLOYS WELL-KNOWN MIMD EXECUTION TO HANDLE BMLAS' IRREGULARITY, AND SEQUENTIAL PREFETCH OF INPUT DATA TO HIDE MEMORY LATENCY. IN MILLIPEDE, HOWEVER, ONE CORELET PREFETCHES A ROW FOR ALL THE CORELETS WHICH MAY STRAY FAR FROM EACH OTHER DUE TO THEIR MIMD EXECUTION. CONSEQUENTLY, A LEADING CORELET MAY PREMATURELY EVICT THE PREFETCHED DATA BEFORE A LAGGING CORELET HAS CONSUMED THE DATA. MILLIPEDE EMPLOYS CROSS-CORELET FLOW-CONTROL TO PREVENT SUCH EVICTION. (4) MILLIPEDE FURTHER EXPLOITS ITS FLOW-CONTROLLED PREFETCH FOR FREQUENCY SCALING BASED ON COARSE-GRAIN COMPUTE-MEMORY RATE-MATCHING WHICH DECREASES (INCREASES) THE PROCESSOR CLOCK SPEED WHEN THE PREFETCH BUFFERS ARE EMPTY (FULL). USING SIMULATIONS, WE COMPARE PNM ARCHITECTURES TO SHOW THAT MILLIPEDE IMPROVES PERFORMANCE AND ENERGY, BY 135% AND 27% OVER A GPGPU WITH PREFETCH, AND BY 35% AND 36% OVER SSMC WITH PREFETCH, WHEN ALL THREE PNM ARCHITECTURES USE THE SAME RESOURCES (I.E., NUMBER OF CORES AND ON-PROCESSOR-DIE MEMORY) AND IDENTICAL DIE-STACKING.